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1
Logic Synthesis Using Synopsys®
Springer US
Pran Kurup
,
Taher Abbasi (auth.)
synthesis
library
clock
synopsys
scan
command
timing
output
input
delay
vhdl
attribute
port
designs
path
compile
technology
constraints
solution
simulation
compiler
figure
verilog
hdl
tools
behavioral
ports
optimization
specified
module
shown
flip
downto
required
designware
netlist
dc_shell
coding
reset
clk
script
specify
hierarchy
flop
signal
cycle
shows
capture
paths
flops
年:
1996
语言:
english
文件:
PDF, 10.28 MB
您的标签:
0
/
0
english, 1996
2
Logic Synthesis Using Synopsys®
Springer US
Pran Kurup
,
Taher Abbasi (auth.)
synthesis
library
clock
scan
synopsys
command
output
vhdl
timing
compile
input
delay
designs
attribute
hdl
path
technology
figure
port
simulation
constraints
flip
compiler
solution
optimization
shown
verilog
dc_shell
module
specified
ports
flops
designware
required
script
hierarchy
netlist
report
edif
flop
paths
coding
signal
values
specify
clocks
commands
methodology
edge
latch
年:
1995
语言:
english
文件:
DJVU, 2.23 MB
您的标签:
0
/
0
english, 1995
3
Logic Synthesis Using Synopsys®
Springer US
Pran Kurup
,
Taher Abbasi (auth.)
synthesis
library
scan
clock
synopsys
command
vhdl
output
timing
compile
designs
input
path
attribute
technology
hdl
figure
port
delay
constraints
simulation
flip
compiler
solution
optimization
shown
module
clk
specified
ports
verilog
flops
designware
required
dc_shell
hierarchy
flop
paths
script
netlist
values
coding
specify
clocks
latch
commands
de_shell
edge
fsm
methodology
年:
1995
语言:
english
文件:
PDF, 18.43 MB
您的标签:
0
/
0
english, 1995
4
Upgrade to Synopsys FPGA Compiler II Synthesis Tool to Maximize Virtex-II Pro Performance
Xilinx
,
Inc.
fpga
compiler
fcii
retiming
synthesis
virtex
synopsys
designers
devices
express
figure
specific
timing
architecture
circuit
designware
xilinx
allows
analysis
automatically
clock
components
engine
fpgas
hdl
inputs
library
optimal
optimization
outputs
pipeline
platform
registers
speed
tools
unique
upgrade
verify
algorithms
blis
capabilities
checker
correctly
datapath
designs
existing
functionality
journal
leda
market
文件:
PDF, 190 KB
您的标签:
0
/
0
5
Upgrade to Synopsys FPGA Compiler II Synthesis Tool to Maximize Virtex-II Pro Performance
Xilinx
,
Inc.
fpga
compiler
fcii
retiming
synthesis
virtex
synopsys
designers
devices
express
figure
specific
timing
architecture
circuit
designware
xilinx
allows
analysis
automatically
clock
components
engine
fpgas
hdl
inputs
library
optimal
optimization
outputs
pipeline
platform
registers
speed
tools
unique
upgrade
verify
algorithms
blis
capabilities
checker
correctly
datapath
designs
existing
functionality
journal
leda
market
文件:
PDF, 190 KB
您的标签:
0
/
0
6
Upgrade to Synopsys FPGA Compiler II Synthesis Tool to Maximize Virtex-II Pro Performance
Xilinx
,
Inc.
fpga
compiler
fcii
synthesis
retiming
virtex
synopsys
designers
devices
express
figure
specific
timing
architecture
circuit
designware
xilinx
allows
analysis
automatically
clock
components
engine
fpgas
hdl
inputs
library
optimal
optimization
outputs
pipeline
platform
registers
speed
tools
unique
upgrade
verify
algorithms
blis
capabilities
checker
correctly
datapath
designs
existing
functionality
journal
leda
market
文件:
PDF, 188 KB
您的标签:
0
/
0
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